FIG. 1 (Prior Art) is a circuit diagram illustrating an integrated circuit 1 mounted on a printed circuit board. Integrated circuit 1 receives power from a voltage supply 2 via conductors 3 and 4, VCC power terminal 5 and ground terminal 6, and internal power and ground buses 7 and 8. Integrated circuit 1 includes a first digital logic element 9 (an input of which is represented here as a capacitive load 10) and a second digital logic element 11. The second digital logic element 11 drives digital logic signals onto the input of the first digital logic element. In the illustrated example, the second digital logic element 11 is a complementary metal oxide semiconductor (CMOS) inverter 12. Inverter 12 includes a signal input lead 13, a P channel pullup transistor 14, an N channel pulldown transistor 15, and a signal output lead 16, a supply voltage terminal 14A, and a ground terminal 15A.
Consider a situation in which inverter 12 switches such that a voltage on capacitive load 10 switches from a digital logic low (for example, zero volts) to a digital logic high (for example, 3.3 volts). Initially, as shown in FIG. 2A, the voltage Vin on the input lead 13 of inverter 12 is a digital logic high. P channel transistor 14 is therefore nonconductive and there is no current draw through P channel transistor 14 from internal power bus 7. Because Vin is a digital logic high, N channel transistor 15 is conductive. Capacitive load 10 is therefore maintained in a discharged state by N channel transistor 15. As shown in FIG. 2B, the voltage V1 across capacitive load 10 is zero while Vin remains low.
The voltage Vin then switches from a digital logic high to a digital logic low as illustrated in FIG. 2A. P channel transistor 14 turns on and N channel transistor 15 turns off. With P channel transistor 14 conductive, a current I1 flows from internal power bus 7 through P channel transistor 14 and charges capacitive load 10. This current I1 is illustrated in FIG. 2C.
There is, however, a short period of time in which P channel transistor 14 is somewhat conductive before N channel transistor 15 has turned off completely. The result is a spike of current I2 that flows from internal power bus 7, from source to drain through P channel transistor 14, from drain to source through N channel transistor 15, and to internal ground bus 8. The resulting current spike is illustrated in FIG. 2D. The total supply current ICC1 drawn by inverter 12 is the combination of currents I1 and I2. This total supply current ICC1 is illustrated in FIG. 2E.
If there were no resistance or inductance between voltage supply 2 and power terminal 5, then this spike of current could be supplied to integrated circuit 1 without dropping the voltage on VCC power terminal 5. There is, however, a resistance and inductance associated with conductor 3. In FIG. 1, this resistance and inductance is represented by resistor 17 and inductor 18. If a spike of current were drawn across resistor 17 and inductor 18, the result would be an undesirable dip in the voltage at VCC power terminal 5. This undesirable dip 19 is illustrated in FIG. 2F.
To prevent such an undesirable dip in the voltage across power and ground terminals 5 and 6, a capacitor 20 is provided near the power and ground terminals. When the short spike of current is demanded by the integrated circuit, capacitor 20 supplies the needed spike of current thus preventing the voltage dip associated with drawing the spike of current across resistance 17 and inductance 18. After the spike of current has been supplied and the current needs of the digital logic element 11 have subsided, the charge given up by capacitor 20 is replenished from voltage supply 2.
The capacitance C needed is determined using the following equation: ##EQU1## The dV in this equation is the magnitude of the permissible voltage dip on internal power bus 7. For this example, the maximum voltage dip permitted on internal power bus 7 is ten percent of the supply voltage VCC. For a VCC of 3.3 volts, dV is approximately 0.3 volts. The dt in this equation is the time duration of the current spike. In a conventional integrated circuit, an inverter switches on the order of 2 nanoseconds. The dt is therefore approximated to be 2 nanoseconds. The ICC1peak is the peak current drawn by a CMOS inverter in a conventional integrated circuit. This peak current ICC1peak can be 2 milliamperes. Accordingly, the capacitance C needed is roughly 7 picofarads (7.times.10.sup.-12 F).
Dielectrics used between metal layers in conventional integrated circuits typically have had dielectric constants of about four. Metal layers have typically been separated by one micron (10.sup.-6 meters) or more. The size of the needed capacitor if realized as a two plate capacitor is given by the following equation: ##EQU2## The k in the equation is the dielectric constant of the dielectric separating the capacitor plates. The .di-elect cons. in the equation is the permittivity constant 8.854.times.10.sup.-12 C.sup.2 Nm.sup.2. The W is the width of the capacitor plates and the L is the length of the capacitor plates. The H is the separation between the capacitor plates. As seen from the equation above, a square (W=L) capacitor of 10 pF would be about 450 microns on a side. Accordingly, the area required to realize the needed capacitor in integrated circuit form has been unrealistically large.
Off-chip discrete capacitors called "bypass capacitors" have therefore been provided on printed circuit boards along with high speed digital integrated circuits. Such a bypass capacitor is placed as close to the integrated circuit as possible so as to bridge the power and ground terminals of the integrated circuit and to supply the integrated circuit with short spikes of current when needed. Capacitor 20 is such a "bypass capacitor".
It is herein proposed that this conventional bypass capacitor technique will be inadequate in certain high current spike situations in the future. This is because FIG. 1 is a simplification. In reality, the internal power and ground buses 7 and 8 on the integrated circuit have significant inherent resistances and inductances.
FIG. 3 is a circuit diagram illustrating the inherent resistance 21 and inductance 22 of the internal power and ground buses 7 and 8. If the time duration of the ICC1 current spike is short enough and the magnitude of the ICC1 current spike great enough, then a significant voltage drop will develop across resistance 21 and inductance 22. As semiconductor processing technology advances and switching speeds increase, such voltage drops are anticipated to become so great that without other corrective action, voltages on internal power buses will spike below required levels and compromise circuit function. A solution is desired.